Future microelectronic circuits will use complicated memory architectures with a total in the range of 10.sup.12 to 10.sup.15 transistors. For financial reasons, one elementary boundary condition is no doubt the desire to use the surface area of each of the memory cells optimally and also to obtain the best possible layout of the memory cells on the semiconductor chip. The size of an individual memory cell, the total number of memory cells and also their wiring extent are significant determining factors for defining the overall surface area of the semiconductor memory.
In particular with regard to the wiring, specific design rules must be followed, i.e., defined, specified instructions relating to the minimum spacing of the individual circuit paths and their contacts with each other. In particular, the size of the individual contacts plays a fundamental role since their lateral dimensions are specified as relatively large in comparison to the corresponding circuit paths..
The invention is thus based on the problem of defining a space-saving layout for a semiconductor memory.